The present invention relates to a semiconductor memory device, and more particularly to a circuit stabilizing a power voltage provided to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an arbitrarily generated decoupling noise.
In DRAMs, cell transistors are connected to word lines through the gates of the cell transistors. When a specific word line is turned on, a plurality of cell transistors operate. A charge charged in a storage node of the cell transistor is shared in bit lines according to the operation of the cell transistor. A sense amplifier is driven, and senses and amplifies the charge shared in the bit lines.
A conventional sense amplifier will be described with reference to FIG. 1.
If a pull-up driving control signal SAEP and a pull-down driving control signal SAEN are transited, or switched, to ‘high’, a pull-up driving transistor N10 and a pull-down driving transistor N12 are turned on.
A power voltage VDD and a ground voltage VSS are respectively applied to a pull-up driving terminal RTO and a pull-down driving terminal SB of a sense amplifier 10 when the pull-up driving transistor N10 and the pull-down driving transistor N12 are turned on. At this time, an equalization circuit 12 is not operated. For reference, the equalization circuit 12 includes a plurality of transistors which operate according to a bit line equalizing control signal BLEQ. The bit line equalizing control signal BLEQ maintains a disabled state when the sense amplifier 10 is driven.
The sense amplifier 10 senses and amplifies the voltage difference between the bit lines BL and BLb when the power voltage VDD and the ground voltage VSS are supplied to the pull-up driving terminal RTO and the pull-down driving terminal SB respectively.
In the sense amplifier 10, when the voltage at bit line BLb is less than the voltage at bit line BL by a predetermined difference ΔV, the PMOS transistor MP1 within the sense amplifier 10 starts to be turned on as a voltage difference Vgs between a gate and a source with respect to the source, (i.e. with respect to the pull-up driving terminal RIO) is generated by ΔV, thereby gradually raising the voltage level of the bit line BL having a bit line precharge voltage level.
When the voltage level of the bit line BL is increased, the PMOS transistor MP2 of the sense amplifier 10 starts to be turned off, and a NMOS transistor MN2 starts to be turned on as the voltage difference Vgs between a gate and a source with respect to the source, (i.e. with respect to the pull-down driving terminal SB) is generated by ΔV, thereby gradually lowering a voltage level of the bit line BLb.
With such positive feedback manner, the PMOS transistor MP1 and a NMOS transistor MN2 are turned on and the PMOS transistor MP2 and a NMOS transistor MN1 are turned off.
Therefore, the sense amplifier 10 operates until the bit line BL reaches the level of the power voltage VDD applied to the pull-up driving terminal RTO, and until the bit line BLb reaches the level of the ground voltage VSS applied to the pull-down driving terminal SB.
Currents I1 and I2 are generated as the bit lines BL and BLb reach the power voltage VDD level or the ground voltage VSS level respectively. These currents flow directly between a power voltage VDD applying terminal and a ground voltage VSS applying terminal and have a maximum peak current value when the voltages applied to the bit lines BL and BLb are equal to VDD/2.
The current generated at this time is the largest peak current in an operation of a DRAM and is also the largest current consuming element.
As described above, when one word line is activated, a plurality of sense amplifiers 10 related thereto are operated. The bit lines BL and BUD are amplified according to the operation of the sense amplifiers 10, the power voltage VDD, and the ground voltage VSS level, or the ground voltage VSS and the power voltage VDD level according to the charge charged in the cell.
At this time, a current level determined according to the operation of the plurality of the sense amplifiers and relating to one word line flows between the power voltage VDD applying terminal and the ground voltage VSS applying terminal. Therefore, the power voltage VDD is temporarily reduced as shown in “A period” of FIG. 2, and the ground voltage VSS is temporarily bounced, or varied as is shown in FIG. 2.
A capacitor MC1 is provided between the power voltage VDD applying terminal and the ground voltage VSS applying terminal to prevent the temporary bouncing. As a result a noise on the power voltage VDD formed by a peak current can be reduced since the instantaneously needed charge is supplied from the capacitor MC1 when the sense amplifier 10 operates.
Meanwhile, a bank compress mode is used in DRAM test to shorten the test time. According to the bank compress mode failure of a cell is not inspected by performing an operation in the unit of one bank, but rather by operating a plurality of banks (for example, four banks) simultaneously. Therefore, in the bank compress mode, data of a plurality of banks are compressed and the compressed data is outputted to one data output port, thereby capable of shortening the test time to ¼ of the existing method.
However, since sense amplifiers of the plurality of banks operate simultaneously in this case, the reduction in the power voltage VDD is increased several fold and thus a row access strobe (RAS) to column access strobe (CAS) delay time tRCD is increased.
The power voltage VDD supplied in DDR2-DRAM is currently 1.8V, but the power voltage VDD supplied in DDR3 is 1.5V. According to this power consumption trend it is expected that the power voltage VDD supplied hereafter will be lowered to less than 1.2V.
As the power voltage VDD is reduced as described above, excessive drops in the power voltage VDD during the operation of the sense amplifier may result in deterioration of AC character and obstruction of device stabilization.